TMS320C6747DZKBA3 456MHz Dual-Core DSP 3648MBPS 32KB L1 Cache 256KB RAM BGA-256 -40°C to +100°C Industrial DSP

TMS320C6747DZKBA3 456MHz Dual-Core DSP 3648MBPS 32KB L1 Cache 256KB RAM BGA-256 -40°C to +100°C Industrial DSP

Features  

• Software Support

– TI DSP/BIOS™

– Chip Support Library and DSP Library

• 375- and 456-MHz TMS320C674x VLIW DSP

• C674x Instruction Set Features

– Superset of the C67x+ and C64x+ ISAs

– Upto 3648 MIPS and 2736 MFLOPS C674x

– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)

– 8-Bit Overflow Protection

– Bit-Field Extract, Set, Clear

– Normalization, Saturation, Bit-Counting

– Compact 16-Bit Instructions

• C674x Two-Level Cache Memory Architecture

– 32KB of L1P Program RAM/Cache

– 32KB of L1D Data RAM/Cache

– 256KB of L2 Unified Mapped RAM/Cache

– Flexible RAM/Cache Partition (L1 and L2)

• Enhanced Direct Memory Access Controller 3 (EDMA3):

– 2Transfer Controllers

– 32Independent DMA Channels

– 8Quick DMA Channels

– Programmable Transfer Burst Size

• TMS320C674x Fixed- and Floating-Point VLIW DSP Core

– Load-Store Architecture with Nonaligned Support

– 64General-Purpose Registers (32-Bit)

– Six ALU (32- and 40-Bit) Functional Units

– Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point

– Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks

– Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle

– TwoMultiply Functional Units

– Mixed-Precision IEEE Floating Point Multiply Supported up to:

– 2SPxSP->SPPerClock

– 2SPxSP->DPEvery Two Clocks

– 2SPxDP->DPEvery Three Clocks

– 2DPxDP->DPEvery Four Clocks

– Fixed-Point Multiply Supports Two 32 x 32-Bit 1 Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples

– Instruction Packing Reduces Code Size

– All Instructions Conditional

– Hardware Support for Modulo Loop Operation

– Protected Mode Operation

– Exceptions Support for Error Detection and Program Redirection

• 128KB of RAM Shared Memory (TMS320C6747 Only)

• 3.3-V LVCMOS I/Os (Except for USB Interfaces)

• TwoExternal Memory Interfaces:

– EMIFA

– NOR(8- or 16-Bit-Wide Data)

– NAND(8- or 16-Bit-Wide Data)

– 16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)

– EMIFB

– 32-Bit or 16-Bit SDRAM with 256-MB Address Space (TMS320C6747)

– 16-Bit SDRAM with 128-MB Address Space (TMS320C6745)

• Three Configurable 16550-Type UART Modules:

– UART0 with Modem Control Signals

– Autoflow Control Signals (CTS, RTS) on UART0 Only

– 16-Byte FIFO

– 16x or 13x Oversampling Option

• LCDController (TMS320C6747 Only)

• TwoSerial Peripheral Interfaces (SPIs) Each with One Chip Select

• Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)

• TwoMaster and Slave Inter-Integrated Circuit (I2C Bus™)

• OneHost-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)

• Programmable Real-Time Unit Subsystem (PRUSS)

– TwoIndependent Programmable Realtime Unit (PRU) Cores

– 32-Bit Load and Store RISC Architecture

– 4KBof Instruction RAM per Core

– 512 Bytes of Data RAM per Core

Applications

• A/VReceivers

• Automotive Amplifiers

• Soundbars

• HomeTheatre Systems

• Professional Audio

• Network Streaming Audio

Description

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .

The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting DSP performance.

INFORMATION

Drawing

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