LATTICE 1048 Device Embedded CPLDs Complex Programmable Logic Devices Chip ISPLSI1048C-50LG/883

1048 device embedded-CPLDs complex programmable logic devices chip from LATTICE ISPLSI1048C-50LG/883

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Features

andbull; HIGH-DENSITY PROGRAMMABLE LOGIC

andmdash; 8000 PLD Gates

andmdash; 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output

Enables

andmdash; 288 Registers

andmdash; High-Speed Global Interconnect

andmdash; Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

andmdash; Small Logic Block Size for Random Logic

andmdash; Security Cell Prevents Unauthorized Copying

andbull; HIGH PERFORMANCE E2CMOSandreg; TECHNOLOGY

andmdash; fmax = 50 MHz Maximum Operating Frequency

andmdash; tpd = 22 ns Propagation Delay

andmdash; TTL Compatible Inputs and Outputs

andmdash; Electrically Erasable and Reprogrammable

andmdash; Non-Volatile E2CMOSTechnology

andmdash; 100% Tested at Time of Manufacture

andbull; IN-SYSTEM PROGRAMMABLE

andmdash; In-System Programmableandtrade; (ISPandtrade;) 5-Volt Only

andmdash; Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

andmdash; Reprogram Soldered Devices for Faster Debugging

andbull; COMBINES EASE OF USE AND THE FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

andmdash; Complete Programmable Device Can Combine Glue

Logic and Structured Designs

andmdash; Four Dedicated Clock Input Pins

andmdash; Synchronous and Asynchronous Clocks

andmdash; Flexible Pin Placement

andmdash; Optimized Global Routing Pool Provides Global

Interconnectivity

andbull; ispDesignEXPERTandtrade; andndash; LOGIC COMPILER AND COMPLETE

ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

andmdash; Superior Quality of Results

andmdash; Tightly Integrated with Leading CAE Vendor Tools

andmdash; Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and isp ANALYZERandtrade;

andmdash; PC and UNIX Platforms

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Description

The ispLSI 1048C/883 is a High-Density Programmable

Logic Device processed in full compliance to MIL-STD-

883. This military grade device contains 288 Registers,

96 Universal I/O pins, 12 Dedicated Input pins, two

Global Output Enables (GOE), four Dedicated Clock

Input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The isp LSI 1048C/883 features 5-Volt in system

programming and in-system diagnostic

capabilities.

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Information :

It is the first device which offers non-volatile

reprogrammability of the logic, and the interconnect to

provide truly reconfigurable systems. Compared to the

ispLSI 1048, the ispLSI 1048C/883 offers two additional

dedicated inputs and two new Global Output Enable pins.

The basic unit of logic on the ispLSI 1048C/883 device is

the Generic Logic Block (GLB). The GLBs are labeled A0,

A1 .. F7 in figure 1. There are a total of 48 GLBs in the

ispLSI 1048C/883 devices. Each GLB has 18 inputs, a

programmable AND/OR/XOR array, and four outputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

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Absolute Maximum Ratings 1

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